The book offers an original view on channel coding, based on a unitary approach to block and convolutional codes for error correction. It presents both new concepts and new families of codes. For example, lengthened and modified lengthened cyclic codes are introduced as a bridge towards time-invariant convolutional codes and their extension to time-varying versions. The novel families of codes include turbo codes and low-density parity check (LDPC) codes, the features of which are justified from the structural properties of the component codes. Design procedures for regular LDPC codes are proposed, supported by the presented theory. Quasi-cyclic LDPC codes, in block or convolutional form, represent one of the most original contributions of the book. The use of more than 100 examples allows the reader gradually to gain an understanding of the theory, and the provision of a list of more than 150 definitions, indexed at the end of the book, permits rapid location of sought information.

Giovanni Cancellieri is full professor of Telecommunications at Polytechnic University of Marche, Italy. His main research activities relate to optical communications, multimedia services, networks, mobile communications, and channel coding. He is a member of various worldwide and European technical associations and standardization bodies.

Generator matrix approach to linear block codes.- Wide-sense time-invariant block codes in their generator matrix.- Generator matrix approach to s.s. time-invariant convolutional codes.- Wide-sense time-invariant convolutional codes in their generator matrix.- Parity check matrix approach to linear block codes.- Wide-sense time-invariant block codes in their parity check matrix.- Strict-sense time-invariant convolutional codes in their parity check matrix.- Wide-sense time-invariant convolutional codes in their parity check matrix.- Turbo codes.- Low density parity check codes.- Binomial product generator LDPC block codes.- LDPC convolutional codes.- Appendix A. Matrix algebra in a binary finite field.- Appendix B. Polynomial representation of binary sequences.- Appendix C. Electronic circuits for multiplication or division in polynomial representation of binary sequences.- Appendix D. Survey on the main performance of error correcting codes.